The present invention relates to a simulation result verification device for performing simulations of semiconductor integrated circuits and verifying the semiconductor integrated circuits from the obtained simulation result.
Recently, there is a demand for high-precision circuit designs for realizing high-performance, highly integrated LSIs, and circuit simulators are playing a key role in such high-precision circuit designs. A circuit simulator performs simulation of LSIs that are to be actually manufactured, based on a netlist representing the circuit information.
FIG. 1 shows a conventional simulation of LSIs. Various kinds of data including a netlist 106, an input vector file 107, a threshold value setting file 108 and a process parameter library 109 are input into a circuit simulator 110. The netlist 106 includes data, which is generated by a netlist output tool 103, on a transistor model library 101 containing the elements necessary for the circuit configuration. FIG. 2A shows the transistor model library 101, which corresponds to transistors and inverters. As shown in FIG. 2B, the input vector file 107 describes the voltages that are input to the input nodes of the circuit at predetermined periods. As shown in FIG. 2C, the threshold value setting file 108 sets threshold values for the nodes to be verified, converting the simulation result into a logic value that is easy to be understood visually. The process parameter library 109 contains files that take the process variations of the elements, such as a transistor, into account.
The circuit simulator 110 outputs a simulation result. A waveform viewer 112 reads and displays the simulation result. FIG. 3 shows a screen of the waveform viewer 112. The waveforms of the input nodes of the circuit are denoted by I/O[0] and I/O[1], and the waveforms of the intermediate nodes are denoted by WL[0] and SL[0]. The waveform viewer shown in FIG. 3 displays the simulation result represented by numeral 301 and a logic value 302 obtained by converting the simulation result into the threshold value. In FIG. 1, numerals 113, 114 and 115 denote the steps of visually verifying the circuit with regard to the displayed contents of the waveform viewer 112, and numeral 116 denotes the completion of the visual verification of the circuit. Numeral 117 denotes a retry when the threshold value settings by the threshold value setting file 108 were improper or when new threshold values are set for the intermediate nodes.
However, there has been the following problem in the prior art.
In the waveform viewer shown in FIG. 3, the set threshold value merely converts the simulation result 301 into the logic value 302, and whether the simulation result 301 is the desired result at time t1 to t2 at a given node can only be confirmed by visual inspection.